[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #17 from Cole Poirier <colepoirier at gmail.com> ---
Additional relevant details taken from
https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L326-340:

```
# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet
# Physical connector pins:
# *** when FEMALE ANGLED (90 deg PMOD) soldered ***
# Jm_n- = Jm_n, Jm_n+ = Jm_n+1
# example: J1_5- is J1_5 phsyical, J1_5+ is J1_6 physical
# *** when MALE VERTICAL soldered ***
# Jm_n+ = Jm_n, Jm_n- = Jm_n+1
# example: J1_5+ is J1_5 physical, J1_5- is J1_6 physical
# Pins enumerated gp[0-27], gn[0-27].
# With differential mode enabled on Lattice,
# gp[] (+) are used, gn[] (-) are ignored from design
# as they handle inverted signal by default.
# To enable differential, rename LVCMOS33->LVCMOS33D
# To enable clock i/o, add this (example):
#FREQUENCY PORT "gp[12]" 25.00 MHZ;
```

Photo of the board showing the pins labelled with numbers 0-27.

> is there anything wrong with the 6 already being brought out?
> genuine question: only looking at the schematic will answer that.

I can't read schematics, can you? Or do I contact the ulx3s developer?

I thought it could be answerd using just the schematics file... can you take a
look at the gpio section of the constraints file which I have linked at the top
of this comment?

It seems like 'PCLK', 'GR_PCLK', and the absence of any qualifier at the right
most end of each of the lines might be significant.

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