[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Fri Oct 23 22:32:31 BST 2020
https://bugs.libre-soc.org/show_bug.cgi?id=517
--- Comment #15 from Cole Poirier <colepoirier at gmail.com> ---
Ok so from the contsraints file:
```
LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 PCLK
LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 PCLK
LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 PCLK
LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 PCLK
LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 GR_PCLK
LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 GR_PCLK
LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3
LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3
LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4
LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4
LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5
LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5
LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6
LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6
```
And the litex platform file:
```
("gpio", 0,
Subsignal("p", Pins("B11")),
Subsignal("n", Pins("C11")),
IOStandard("LVCMOS33")
),
("gpio", 1,
Subsignal("p", Pins("A10")),
Subsignal("n", Pins("A11")),
IOStandard("LVCMOS33")
),
("gpio", 2,
Subsignal("p", Pins("A9")),
Subsignal("n", Pins("B10")),
IOStandard("LVCMOS33")
),
("gpio", 3,
Subsignal("p", Pins("B9")),
Subsignal("n", Pins("C10")),
IOStandard("LVCMOS33")
),
```
does this imply that another 3 gpio record can be added? like so:
```
("gpio", 4,
Subsignal("p", Pins("A7")),
Subsignal("n", Pins("A8")),
IOStandard("LVCMOS33")
),
("gpio", 5,
Subsignal("p", Pins("C8")),
Subsignal("n", Pins("B8")),
IOStandard("LVCMOS33")
), ("gpio", 4,
Subsignal("p", Pins("C6")),
Subsignal("n", Pins("C7")),
IOStandard("LVCMOS33")
),
```
And should these newly added gpio pins be the pins we use for the JTAG jumper
cables?
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