[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #12)

> B11 is the name of one of the FPGA's solder balls directly on the chip's
> package, (B row/column 11 column/row). look up the datasheet for your board
> to find out the mapping between solder balls and header pins.

ahh brilliant, that's very helpful jacob, that wouldn't have occurred to me
that it was the actual ECP5 pad.

ah wait.. yeah of course it is, because nextpnr-ecp5 doesn't know about PCB
layouts, it only knows about, well... the ECP5.

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