[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #6 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
>
> comment #1.
> 
> vvvvv
> which means: someone's going to have to to through this file:
> https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/
> ulx3s.py#L72
> (which defines the pin allocations)
> ^^^^^

Already did this. What I don't know how to do is estaplish the relationship
between this      

("gpio", 0,
    Subsignal("p", Pins("B11")),
    Subsignal("n", Pins("C11")),
    IOStandard("LVCMOS33")
),

and the number on the physical board. Which of the pins numbered 0 through 27
is gpio_0 or B11 or C11?

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