[Libre-soc-bugs] [Bug 519] Get output from ulx3s serial port to show up in minicom

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=519

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
so, to reiterate:

* variants specify what is permitted
* sim.py, versa_cp5.py, may request a variant
* verilog file must provide the signals used by the variant.

you need to check *the full chain* by looking at the source and the output from
each command.

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