[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

--- Comment #59 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
 139     sim.add_sync_process(wrap(icache_mmu_sim(mmu)))
 140     sim.add_sync_process(wrap(wb_get(icache, "ICACHE")))

right.

ok.

the default dict here you have left it as mem_default.

that mem_default is set up to answer an example taken from gem5-power which is
*specifically* for dcache.

it has absolutely no entries for instruction cache reading whatsoever 

also this is not the test that needs to be written (yet).

the test that needs to be written - *still using wb_get when taking two
arguments one of which is a mem dict* - is to test the icache, *not the icache
using the mmu*

in other words look at icache.py unit test and instead of the SRAM add the
wb_get as the sync process with a nicely pre-prepared mem dict (that contains
100 randomly created keys and values)

later we can and will do "icache-with-mmu" but only after doing "icache"
because if we have not tested icache how can we tell what is faulty if the
with-mmu fails?

one test at a time.

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