[Libre-soc-bugs] [Bug 515] confirm that it is possible to upload into SRAM via JTAG

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=515

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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             Blocks|                            |383
           Priority|---                         |High

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
jtagremote client-server demo / unit test showing how this is done

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap_srv.py;hb=HEAD

DMI registers (DMI.CTRL) showing which bits need to be written to call "halt",
stop, and start.  also probably a good idea to send "icache sync".

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/dmi.py;hb=HEAD#l30

note that after sending JTAG DMI READ or WRITE-READ the DMI address is
*automatically* incremented to the next DMI address.  this to save having to
repeatedly set the DMI address and thus saving JTAG bandwidth.

the same thing is done for JTAG WB.


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=383
[Bug 383] Complete first functional POWER9 Core
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