[Libre-soc-bugs] [Bug 511] New: Add a test of IO pins to debug/test/test_jtag_tap.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=511

            Bug ID: 511
           Summary: Add a test of IO pins to debug/test/test_jtag_tap.py
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: normal
          Priority: Normal
         Component: Source Code
          Assignee: colepoirier at gmail.com
          Reporter: colepoirier at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org
            Blocks: 383
   NLnet milestone: NLNet.2019.10.Wishbone
    parent task for 383
 budget allocation:

http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000697.html


``` lckl
Add a test of IO pins to debug/test/test_jtag_tap.py.  i *think*
these are "standard-defined JTAG behaviour".  need to work out the
code (or find IEEE JTAG documentation)

some commands here:
https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/c4m/nmigen/jtag/tap.py#L344

and here you can see the Muxes being created:
https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/c4m/nmigen/jtag/tap.py#L443

JTAG Boundary scan it's officially called.
https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/test/nmigen/cocotb/controller/test.py#L99"

yep that needs converting to nmigen.
```


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=383
[Bug 383] Complete first functional POWER9 Core
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