[Libre-soc-bugs] [Bug 509] divwe. causing assertion failure in handle_comparison

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=509

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|CONFIRMED                   |RESOLVED
         Resolution|---                         |FIXED

--- Comment #5 from Jacob Lifshay <programmerjake at gmail.com> ---
Fixed.
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=ca2fad49abde84d356ad31d3a8a6ae65db63afb4

I'm assuming `overflow` is probably not the only variable that needs to be in a
particular order, so I left a TODO comment in src/soc/decoder/isa/caller.py:

REG_SORT_ORDER = {
    # TODO (lkcl): adjust other registers that should be in a particular order
    # probably CA, CA32, and CR
    "RT": 0,
    "RA": 0,
    "RB": 0,
    "RS": 0,
    "CR": 0,
    "LR": 0,
    "CTR": 0,
    "TAR": 0,
    "CA": 0,
    "CA32": 0,
    "MSR": 0,

    "overflow": 1,
}


def create_args(reglist, extra=None):
    regset = OrderedSet(reglist)
    retval = []
    for reg in regset:
        retval.append(reg)
    retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
    if extra is not None:
        return [extra] + retval
    return retval

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