[Libre-soc-bugs] [Bug 507] ls180 asic needs an ioring, pads need defining and connecting

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=507

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #13)

>   Thanks, now it will take two or three days for me to adapt
>   the plugin.

jean-paul if you can review this and if we do not need different clock
connection rules for jtag_tck etc then it is done for now, because Staf
mentioned we can only do a single 3.3v and a single 1.8v due to ESD.

https://bugs.libre-soc.org/show_bug.cgi?id=506#c17

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