[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
these are now defined by pinmux ls180 spec

https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/ls180.py;hb=HEAD

the nmigen JTAG module sets up IOconn instances and also takes a pinset.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD

the pinset dictionary currently hardcoded as dummy_pinset() is now
autogenerated by the pinmux

Issuer creates one of these JTAG modules and through the pinset creates a suite
of ports (JTAG core and io pads) which end up in the public interface in the
verilog module.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;hb=HEAD#l83


using the EXACT same pinmux Pin definitions, Litex LS180Platform creates two
sets of IO resources, one for JTAG pads one for JTAG core and connects up the
core ones to the test_issuer verilog with make_jtag_conn

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/libresoc/core.py;hb=HEAD#l236

where a "normal" litex core would connect direct to the *platform* IO resource,
because JTAG has been connected to that litex instead connects to the *CPU* IO
resource(s) which were routed via the JTAG IOconn MUXes and back out again
through test_issuer

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;hb=HEAD#l431

in the coriolis2 layout the ioring is created by using once again the EXACT
same pinmux spec to create a JSON file with the mappings between LITEX
peripheral names and coriolis2 IO pin names

https://git.libre-soc.org/?p=soclayout.git;a=blob;f=experiments9/coriolis2/ioring.py;hb=HEAD

in this way we get automated centrally specified IO without getting into a
manual duplication mess.

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