[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

--- Comment #29 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #28)
> ah. right.  not a bug at all.  turns out the SRAM WB module was not properly
> WB spec compiliant.  sigh.

(In reply to Luke Kenneth Casson Leighton from comment #27)
> (In reply to Cole Poirier from comment #26)
> > Fantastic! Thanks for fixing it!
> 
> it was after looking at the gtkwave i noticed that the SRAM module only sent
> ack every other cycle.
> 
> but... the r.store_row was advanced *even when no ack had yet come in*

In-light of the above comment #28, do I have to do something to the SRAM or
have you already done it?

> > Do you want me to work on the
> > memory-dictionary test utility that we discussed yesterday?
> 
> yes and do the comment corrections that you missed.

Sorry I'm not sure what you're referring to here? Is this in reference to my
commit message saying 'fixed bugs raised in bugzilla comments' without
providing the url to the exact comment numbers?

> a dictionary memory test based on wb_get will allow very large addresses to
> be sent and also lots of them.
> 
> if you do several thousand this will create some cache flush (evictions) and
> we will find potential errors that might otherwise be missed.

Very cool, I'll give it a go today.

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