[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #58 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok the table's fine, there is however duplicate "zero wires" entries.

remove this, replace with individual lines:

* ensure power is disconnected from FPGA
* ensure STLINKV2 USB is disconnected
* ensure FPGA USB is disconnected

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