[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #57 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #56)
> Hey Luke, tried reaching you on irc yesterday but haven't heard from you
> there, so I thought I should notify you here, via the bug tracker that I did
> what you've asked for and now await your review and feedback.

excellent, yes, sorry, been mostly away from the laptop for... about a week.

suggest modifying the checklist to split into three (four):

1) connect male-to-female colour on STLINKv2
2) connect female-to-female on ulx3s
3) same for versa ecp5
4) starting with "ensure power is disconnected" wire up colours, then finally
describe power-up sequence.

and to remove the "don't" table, downgrade it to conversational statements and
advice.  we do not want "negative don't take action X statements" in a
checklist table, ever.

-- 
You are receiving this mail because:
You are on the CC list for the bug.