[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #59 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #58)
> ok the table's fine, there is however duplicate "zero wires" entries.
> 
> remove this, replace with individual lines:
> 
> * ensure power is disconnected from FPGA
> * ensure STLINKV2 USB is disconnected
> * ensure FPGA USB is disconnected

Ok done. Do you think it's better to have the FPGA and the corresponding
STLINKv2 connections in the same line of the same table or following from this:

1) connect male-to-female colour on STLINKv2
2) connect female-to-female on ulx3s

Break it down even further into one table for each fpga wiring, and a shared
table for wiring those colours to the STLINKv2?

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