[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
| 0 | 1  | 2 3 4 | | 567.8 | 9ab  | c d e | f |
| 1 | o2 |  RT   | | 010.0 | RB|0 | offs  | 1 | addi.
| 1 | o2 |  RT   | | 010.1 | RB|0 | offs  | 1 | addis.

these i'm reluctant to go entirely immediate in bits 2-4 because when
RB=0 it encodes "li RT, #imm" even though the immediate is only in
the range 0-15 for addi and -8 to 7 for addis.

(actually a better encoding there would be just addis, why has nobody
noticed a massive overlap between addis and addi before in OpenPOWER
ISA v3.0B????)

for each it miiight be ok to use 1 more bit (range -16 to +15) by reducing
RT down to 2 bits (regs r0-r3)

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