[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
oo i just had an idea.  in the immediates (aadi, addis, cmpwi, cmpdi) allow RT
in the 16 bit mode *but*: when RT==RA shift the immediate by RT.

with RA/RT being 3 bit this will allow access to hword/word/dword-aligned
constants and more.  the encoding is similar to FP, in that when RT==RA it
becomes an exponent.

interestingly with RT==RA==0 covering all other cases of RT==0, RA!=0, we have
a brownfield encoding opportunity.

i am reluctant to suggest using POSIT encoding here sigh.

-- 
You are receiving this mail because:
You are on the CC list for the bug.