[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Nov 16 17:08:40 GMT 2020


--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
oo i just had an idea.  in the immediates (aadi, addis, cmpwi, cmpdi) allow RT
in the 16 bit mode *but*: when RT==RA shift the immediate by RT.

with RA/RT being 3 bit this will allow access to hword/word/dword-aligned
constants and more.  the encoding is similar to FP, in that when RT==RA it
becomes an exponent.

interestingly with RT==RA==0 covering all other cases of RT==0, RA!=0, we have
a brownfield encoding opportunity.

i am reluctant to suggest using POSIT encoding here sigh.

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