[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #21)
> (In reply to Luke Kenneth Casson Leighton from comment #18)
> > ok do you want to have a go at reencoding the FP section? i have not studied
> > it nearly as much as the INT v3.0B so you would likely do a better job than
> > me anyway.
> 
> Sure, though I'll probably put that off till tomorrow.

no problem at all.  some gotchas:

* i've re-orged the tables so that bits 567.8 are now major.minor
* major 0b011 is designated "sub" across both Arith and FP
  - 0b011.0 is arith sub./neg./cmp (producing CR0 unconditionally)
  - 0b011.1 is FP fsub./fneg.      (producing CR1 unconditionally)
* the 0b110 major opcode is entirely dedicated to FP

> > if you mean right at the top, the ldi, then at the cost of all ldi/sti being
> > this:
> 
> I mean we could have the particularly common instructions take up 2 opcode
> slots, using 1 of the opcode bits for an immediate bit.

space is so ridiculously tight that several compromises are taken.  2
opcode slots means "dropping mul or neg" for example

> We could then use the free space from the other instruction as a second
> opcode field to allow encoding the instruction moved to make room for the
> two opcode slots.
> 
> Or something like that.

i see where that's going: where they'd have RT=RA (add RT,RT,RA format)

if it wasn't for the 10-bit => 16-bit thing i'd say "great", straight
away.  however the way i see it is that if trying to jam immediates
into 10-bit the pressure on the major opcode space is so great that
i prioritised non-immediates with the exception of branch (and even
there, nop and illeg are encroaching on that)

then, only the 16-bit immediate modes kick in when bits 0 and f are 0b11
which... looking at the latest version bit 8 (minor opcode) i *think*
might aslso be free to allocate to offset... it is!

oo exciting there's a free major immediate-qualified opcode, ooo!
any suggestions?  extend addi? add sti / fsti...

> If we need to, we could have load instructions have 1 more bit of immediate
> than store instructions, since load instructions are more common.

... ah yeah, ok, i added sti / fstwi back in

> > another way to extend the range of immediates: align them.  ldi must be 8
> > byte aligned, lwi must be word aligned.
> > not unreasonable.
> 
> Exactly what RVC does :)

*sotto voice* where i got the idea from

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