[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #21 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #18)
> ok do you want to have a go at reencoding the FP section? i have not studied
> it nearly as much as the INT v3.0B so you would likely do a better job than
> me anyway.

Sure, though I'll probably put that off till tomorrow.

> > except that using those bits instead to encode more immediate bits for ld,
> > addi, st most likely gives more advantage.
> 
> ah i mean in the arithmetic section (the trick of cmp applies/applied) which
> has no immediates.
> 
> if you mean right at the top, the ldi, then at the cost of all ldi/sti being
> this:

I mean we could have the particularly common instructions take up 2 opcode
slots, using 1 of the opcode bits for an immediate bit.

We could then use the free space from the other instruction as a second opcode
field to allow encoding the instruction moved to make room for the two opcode
slots.

Or something like that.

If we need to, we could have load instructions have 1 more bit of immediate
than store instructions, since load instructions are more common.

> another way to extend the range of immediates: align them.  ldi must be 8
> byte aligned, lwi must be word aligned.
> not unreasonable.

Exactly what RVC does :)

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