[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Nov 15 03:04:54 GMT 2020


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)
> one important note, in floating-point 0 - x does not give the same results
> as -x
> the values you get for 0 - 0 depend on the sign of the two inputs and on the
> rounding mode.
> So, I'd instead suggest combining fneg with fmr.

hm hm fmr explicitly requires 2 registers (src, dest).  in 10-bit mode there's
so little space that the only possible candidate for dropping and replacing
with fmr. would be fmul.

fmul (and fdiv?) could then be made available only in 16-bit mode (not

what do you think of changing fmul to have RA==0b000 to indicate "fmr."
(and leave fsub. to have RA==0b000 to indicate "fneg.")?

i am currently just arbitrarily experimenting, there's no backup studies
to show statistical preference for one combination over another, here

> An additional idea, if we have to use an additional 16-bit instruction to
> enter 16-bit mode: it's common to have just 1 32-bit (or wider) instruction
> in a sequence of 16-bit instructions, it might be a good idea to have a
> limited subset of 16-bit instructions have additional info included to tell
> the processor to exit 16-bit mode for just 1 instruction, then reenter
> 16-bit mode without needing to use an enter-16-bit-mode instruction.

it's... doable.  the instruction groups with a spare bit are:

* FP
* Logical
* Arithmetic
* System sc/rfid

LD i wanted to reserve the 2 spare bits for width, update and other modes.

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