[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> (In reply to Jacob Lifshay from comment #2)
> > one important note, in floating-point 0 - x does not give the same results
> > as -x
> > 
> > the values you get for 0 - 0 depend on the sign of the two inputs and on the
> > rounding mode.
> > 
> > So, I'd instead suggest combining fneg with fmr.
> 
> hm hm fmr explicitly requires 2 registers (src, dest).  in 10-bit mode
> there's
> so little space that the only possible candidate for dropping and replacing
> with fmr. would be fmul.

Will require some thought.

> 
> fmul (and fdiv?) could then be made available only in 16-bit mode (not
> 10-bit)
> 
> what do you think of changing fmul to have RA==0b000 to indicate "fmr."
> (and leave fsub. to have RA==0b000 to indicate "fneg.")?
> 
> i am currently just arbitrarily experimenting, there's no backup studies
> to show statistical preference for one combination over another, here

Yeah, we need to at least check instruction statistics on some integer code.

> 
> > An additional idea, if we have to use an additional 16-bit instruction to
> > enter 16-bit mode: it's common to have just 1 32-bit (or wider) instruction
> > in a sequence of 16-bit instructions, it might be a good idea to have a
> > limited subset of 16-bit instructions have additional info included to tell
> > the processor to exit 16-bit mode for just 1 instruction, then reenter
> > 16-bit mode without needing to use an enter-16-bit-mode instruction.
> 
> it's... doable.  the instruction groups with a spare bit are:
> 
> * FP
> * Logical
> * Arithmetic
> * System sc/rfid

What are system instructions doing in 16-bit mode?!! they should be 32-bit
only, they are very uncommon (with the possible exception of m[ft]ctr, m[ft]lr
and maybe m[ft]cr).

> LD i wanted to reserve the 2 spare bits for width, update and other modes.

it will require some stats, but I think update can be left for 32-bit only.

Some other instructions that should be 32-bit mode only are the less commonly
used CR instructions, only a few of them are commonly used. You can probably
cram a addi instruction in there instead, those are very common, and it can
double as mv.

-- 
You are receiving this mail because:
You are on the CC list for the bug.