[Libre-soc-bugs] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i had to change decoder/isa/fixedarith.py to this, to get it to work:

    @inject()
    def op_divw(self, RA, RB, RT):
        dividend = RA[32:64]
        divisor = RB[32:64]
        RT[32:64] = dividend // divisor
        RT[0:32] = undefined[0:32]
        return (RT,)

fixedarith.py is auto-generated by pywriter.py

oh, i also updated the parser so that it will output floordiv not div,
and updated SelectableInt so that it has an __floordiv__ function.  the
parser was previously outputting this:

        RT[32:64] = dividend / divisor

it will be necessary to check the behaviour of signed/unsigned and
potentially code up the correct behaviour in SelectableInt.__mod__
and SelectableInt.__floordiv__:

>>> 5//0
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
ZeroDivisionError: integer division or modulo by zero
>>> 

>>> -1 % 0
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
ZeroDivisionError: integer division or modulo by zero
>>> 


yes, definitely.  we can't have that.  those will need to be caught in
SelectableInt and the correct value returned.


also this, from the spec for modsw:

If an attempt is made to perform any of the divisions
0x8000_0000 % -1
<anything> % 0

and for modsd:

If an attempt is made to perform any of the divisions
<anything> % 0 0x8000_0000_0000_0000 % -1

that's likely going to have to be special-cased as well, or at least tested
and we work out what is supposed to be put into RT.  interestingly these
do *not* result in overflow flags being set.

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