[Libre-soc-bugs] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
jacob i've added soc/simulator/test_sim_div.py and immediately ran into
both pseudocode and spec issues.  both divsw and modsw contain a
"minus" symbol following the setup of the divisor:

    divisor [0:31] <- (RB)[32:63]-

this has no explanation in the spec notation as to what it means.
also, the variables "dividend" and "divisor" do not exist.  given
that this is the pseudocode we're talking about - the actual spec -
i am reluctant to make significant modifications.  we may however
have to.

i have already made this change:

    RT[0:31 ] <- undefined

-->

    RT[0:31 ] <- undefined[0:31]

however i am not happy with it.

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