[Libre-soc-bugs] [Bug 375] Finding new project members who can help with complex detailed work such as LDSTCompUnit

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=375

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #8)

> Sorry, I thought that's what you said we needed when we spoke on sunday, I
> misunderstood. Which area or which NLNET grant should I be 'targeting'?

under this bugreport? this one is HDL engineers (the video one is assembly code
writers however it needs binutils and at least the ISACaller simulator or "a"
simulator to support SV)

for this bugreport we therefore need people with as many of these as possible:

* python
* gate level design (circuits or ASICs)
* FPGA programming
* nmigen, verilog, VHDL or Chisel3
* team collaboration and communication
* respect for Libre Project development practices
* technical writing skills
* software engineering background or equivalent (which is very different from
"computer science degree")
* electrical engineering
* self-taught (autodidact) capacity

-- 
You are receiving this mail because:
You are on the CC list for the bug.