[Libre-soc-bugs] [Bug 407] XICS interrupt controller is needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=407

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #12)
> master/LoPAR/ch_interrupt_controller.xml) That deals with PCIE interrupts?
> Sorry I'm still a little confused...

so the interrupt wires from PCIe would go *into* the source vector XICS_ICS.

e.g. bit 5 would be PCIe device 1's hardware interrupt wire.  or however it is
done.

bit 6 of the XICS source would be connected e.g. to SPI0 and so on.

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