[Libre-soc-bugs] [Bug 407] XICS interrupt controller is needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=407

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #9)
> (In reply to Luke Kenneth Casson Leighton from comment #8)
>  
> > this again is the virtualisation of interrupts, not the actual interrupts. 
> > cinsequently whilst the same registers appear (CPRR, PIPR) there's nothing
> > about those.
> > 
> > my feeling is that the spec has never been released: the qemu XICS code for
> > example is written *by* someone at IBM who had internal access to it.
> 
> Oy gevalt! Such a headache, although I think Jacob may have found what we
> are looking for:... will edit with reference to mailing list archives once
> they are up-to-date enough to include jacob's mail.
> 
> ```
> from: Jacob Lifshay <programmerjake at gmail.com>
> to: Libre-RISCV General Development <libre-riscv-dev at lists.libre-riscv.org>
> date: Jul 28, 2020, 9:51 AM PDT
> subject: Re: [libre-riscv-dev] how do we test external interrupts?
> 
> I found what looks like the reference source:
> in
> https://github.com/torvalds/linux/blob/
> ab02b61f24c76b1659086fcc8b00cbeeb6e95ac7/Documentation/virt/kvm/devices/xics.
> rst
> > This device emulates the XICS (eXternal Interrupt Controller
> Specification) defined in PAPR.
> 
> https://en.wikipedia.org/wiki/Power_Architecture_Platform_Reference
> 
> https://github.com/OpenPOWERFoundation/Linux-Architecture-Reference
> 
> Jacob
> ```
> 
> I think this is the key part:
> 
> https://github.com/OpenPOWERFoundation/Linux-Architecture-Reference/blob/
> master/LoPAR/ch_interrupt_controller.xml
> PowerPC External Interrupt Architecture:
> ```
> <chapter  xmlns="http://docbook.org/ns/docbook"
>           xmlns:xl="http://www.w3.org/1999/xlink"
>           xml:id="dbdoclet.50569331_37856"
>           version="5.0"
>           xml:lang="en">
>   <title>Interrupt Controller</title>
> 
>   <para>This chapter specifies the requirements for the LoPAR interrupt
>   controller. Platforms may chose to virtualize the interrupt controller or
> to
>   provide the PowerPC External Interrupt option. </para>

no it's not that one - XICS is like the PLIC for RISC-V.  it's the central
(generic) "hub" for interrupts and defines the layout of in-memory registers.

for example for the source layer (microwatt xics.vhdl):

-- Register map
    --     0  : Config
    --     4  : Debug/diagnostics
    --   800  : XIVE0
    --   804  : XIVE1 ...
    --
    -- Config register format:
    --
    --  23..  0 : Interrupt base (hard wired to 16)
    --  27.. 24 : #prio bits (1..8)
    --
    -- XIVE register format:
    --
    --       31 : input bit (reflects interrupt input)
    --       30 : reserved
    --       29 : P (mirrors input for now)
    --       28 : Q (not implemented in this version)
    -- 30 ..    : reserved
    -- 19 ..  8 : target (not implemented in this version)
    --  7 ..  0 : prio/mask


and for the presentation layer there's something similar.

so the interrupt wires come in from a "source" (a single bit,
each given a number), and it is possible to set the individual
priority (by writing to the XIVEnnn register).

then the "presentation" layer receives a notification about one
of those, and generates - to the core - a *single* interrupt to
say "please come and look at the presentation layer registers
XIRR and MFRR to find out which one of the source interrupts
has occurred".

from the microwatt source code, _reading_ the XIRR register actually
clears the interrupt.

so that's how it fits together.

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