[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #36 from Jean-Paul.Chaput at lip6.fr ---

Thanks for the hints.

Just to let you know, I'm working on the floorplan, so I'm studying closely
the structure of the issuer netlist, as created after going through Yosys.

I've noticed something "unusual" (in my experience in hierarchical ASICs),
some models have blocks and a few standard cells (relatively speaking).
When processed, flat, this is not a problem, but if we want to place
each block, then the top level, the placement of those stray cells
may be difficult (meaning: far from optimal).

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