[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #140 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Samuel A. Falvo II from comment #138)
> (In reply to Luke Kenneth Casson Leighton from comment #137)
> >                  # check EE (48) IR (58), DR (59): PR (49) will over-ride
> > -                comb += [
> > -                    Assert(msr_o[48] == (srr1_i[48] | srr1_i[48])), # EE
> > -                    Assert(msr_o[58] == (srr1_i[58] | srr1_i[58])), # IR
> > -                    Assert(msr_o[59] == (srr1_i[59] | srr1_i[59])), # DR
> > -                ]

it should have been srr[49] i.e. the PR field at the end, anyway.

see what happens if you do PR = field(srr_i, 49) then use that shortened
variable name.

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