[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #25)
> (In reply to Luke Kenneth Casson Leighton from comment #24)
> > (In reply to Cesar Strauss from comment #23)
> > 
> > > I also sent a trimmed test case, without the shift state, which still
> > > produces the issue.
> > 
> 
> As it turns out, the behavior of cxxsim is consistent with it doing an
> implicit Settle() after every yield.

interesting.  (i saw on the nmigen tracker).

> The issue is not fixed yet, so I'd avoid relying on cxxsim results for the
> time being.

ok

> > fantastic it came up in irc on freenode earlier
> 
> Interesting place.

yes.

> I joined the channel as "cesar".

we really should run our own irc channel

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