[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #129 from Samuel A. Falvo II <kc5tja at arrl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #126)
> i will commit this shortly.  do you note two things:
> ...
> +    start = 63 - start
> +    end = 63 - end
> +    # XXX must do the endian-reversing BEFORE doing the comparison
> +    # if done after, that instead asserts that (after modification)
> +    # start *MUST* be greater than end!
>      if start >= end:
>          raise ValueError(
>              "start ({}) must be less than end ({})".format(start, end)
>          )
> -    start = 63 - start
> -    end = 63 - end
>      return slice(end, start + 1)

This is a bug.

Consider: if you perform the mapping prior to the if-statement, if you invoke
field_slice(x, 0, 31), then by the time the if-statement executes, start=63 and
end=32.  start >= end will always be true for every valid use of the field()
call.

Putting the error-check prior to the mapping does two things:
1. It enforces correct usage of the function, and,
2. Gives correct diagnostics when the exception is raised, in terms of the
correct abstraction (IBM's "MSB 0" notation, as I learned last night that's
what it's called, per Wikipedia).

This will need to be switched back.

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