[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #61 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
sorry, jacob: i tried building pia (see comments in #433) and it was
impossible to follow.

i've therefore reverted the commit that adds it as a critical dependency
because it completely terminates all and any possibility of running
not just the test_pipe_caller.py unit test but everything else in upstream
testing as well (test_issuer.py etc).

i will try to reproduce the divdeu bug without pia.

also, two things:

* please don't add "typing" directly to .py files.  add them to a .pyi file
  instead.

* remember to keep lines to below 80 chars several additions were not, which
  made reviewing the diffs harder than they should be:

-            with self.subTest(check="pia", sim_o=sim_o,
pia_result=str(pia_resu
lt)): <<<---

* remember to single-purpose commit.  modifications to ISACaller had
  been added (without an explanatory comment) that had nothing to do
  with the addition of pia itself.

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