[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #116 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #115)

> > Per your own advice, I was to translate the pseudocode found in the specs
> > into formal properties.  The pseudocode itself refers to raw bit fields of
> > registers by number.
> 
> ah yes i see.  ok

didn't finish.

i didn't clarify: i meant, only the accessors to MSR and SRR1.  not the LEV
field, TO field etc.

sorry.

the instruction opcode fields are not part *of* the pseudocode, they are used
*by* the pseudocode.

some fields such as sh, me, mb, from ShiftRotate, are "constructed" (IBM
actually got these wrong in the spec!)

manual bitinversion combined with manual reordering would be so unclear and so
confusing that i cannot countenance it.

at least by using the Decode Fields/Forms that reduces confusion there.

for registers such as MSR etc yes we coukd do with something better.

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