[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #110 from Samuel A. Falvo II <kc5tja at arrl.net> ---
(In reply to Samuel A. Falvo II from comment #108)
> This seems like a gaping hole in the spec, and I'd argue it needs top
> priority for resolution by the OpenPower group.

To add two more things to this train of thought:

1. If bit 0 of a field is the least significant bit, just written to the left
of the most significant bit, then why do we bother with the 63-x computation at
all?  It shouldn't matter how the bits are printed on paper.

2. This implies that some 32-bit registers (those which are documented using
bits ranging from 32 to 63) actually occupy the upper half of a GPR when moved,
not the lower-half.

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