[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|colepoirier at gmail.com       |kc5tja at arrl.net

--- Comment #104 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/trap/main_stage.py;h=119d3e918be408472cfe0b428fe3f3ea201c2c71;hb=5e73a60c7beb52480dcf73469f597aa28b845227#l267

 266                 # if the opcode's LEV sub-field is equal to 1.
 267                 trap_to_hv = Signal(reset_less=True)
 268                 lev = Signal(6, reset_less=True)
 269                 comb += lev.eq(op[31-26:32-20])
 270                 comb += trap_to_hv.eq(lev == Const(1, 6))

samuel: two things.

1. we are following microwatt, which has not implemented hypervisor.  therefore
if doing LEV at all this should be an illegal instruction (which is tested and
raised in PwerDecode2, not here) however this needs checking as there is
something odd about SC LEV !=0

2. direct field bit accessing of op.insn is a "no-no".  it is impossible to
understand and read.  using fields.FormSC.LEV is the "correct" convention. 
only code from microwatt that has not been decoded yet has "direct" bit access
(bit 20 of insn for example)

3. the bit fields are in *PowerISA* order and need reversing: this is why we
use DecodeFields, why FieldSelectableInt exists.

4. the only reason the trap formal proof assertion is correct against this
newly-added code is because *both are the wrong bit order*

i will update code-comments to reference here.

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