[Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=421

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit bb40a98bcbce1bab7eb86cf4ba0d1d3788cd86ca (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Jul 22 13:42:53 2020 +0100

    code-shuffle, add comments

samuel i've added some code-comments and shuffled the Asserts, which allow
humans to read the pseudo-code (in line order), and stand a chance of
verifying it.

the use of the actual field names (MSR.HV) *actually prevents* this
rather than aids and assists in it, because the soc.consts file containing
the MSR numbering class has to be opened, side-by-side with proof_main_stage.py
*and* with the spec PDF...

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