[Libre-soc-bugs] [Bug 435] New: PC and MSR need to be in the "state" (Decode2Execute1Type)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=435

            Bug ID: 435
           Summary: PC and MSR need to be in the "state"
                    (Decode2Execute1Type)
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

to save on regfile ports, PC and MSR need to be pased in to
PowerDecode2 (MSR already is), and put into Decode2Execute1Type
then copied into XXX_input_record (CompXXXOpSubset) as appropriate.

this affects branch, trap and spr pipelines.

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