[Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=421

--- Comment #19 from Samuel A. Falvo II <kc5tja at arrl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #18)
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/trap/formal/
> proof_main_stage.py;h=48221f2945dd115b31bf34dfc7fb5b3919c1d601;hb=HEAD#l28
> 
> should that be +1 on 63-start i.e. 64-start because python slice?

Yes, thank you.  Good catch.

I'm noticing that the trap logic does not drive o.msr.ok; should it?  According
to the SC pseudo-code, MSR is updated, along with SRR0 and SRR1.

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