[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #14 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)
> interesting!  a "yield" was missing which was only caught by cxxsim

I tried running cxxsim by "git checkout cxxsim" in nmigen, updating yosys to
latest git master, and setting "cxxsim = True". But it is giving me weird
waveforms (signals are changing on the falling edge of the clock).

> commit fc256a3df6502d725131a3aa979c2a88aa695d3d (HEAD -> master)
> Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> Date:   Sun Jul 19 15:53:36 2020 +0100
> 
>     fix bug in alu_fsm.py found by cxxsim: missing one cycle hold of ready_i

There was already a one cycle hold of ready_i.
235   # signal readiness to receive data
236   yield dut.n.ready_i.eq(1)
237   yield

You added another one, and now there are two.
244   # must leave ready_i valid for 1 cycle, ready_i to register for 1 cycle
245   yield

Looking at the waveform, I can see that, after the last transfer, ready_i is
held for one extra cycle, which is wrong.

What did you see in cxxsim? Is it possible that cxxsim is giving wrong results?

If the simulation stops too soon, we can add an extra yield, after receiving
the last result.

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