[Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=421

--- Comment #4 from Samuel A. Falvo II <kc5tja at arrl.net> ---
I must be doing something stupifyingly stupid.  I'm just not able to satisfy
the properties for the RFID instruction.

I can only guess that I'm unable to understand the order of precedence by which
bits in the output MSR are set.  Several bits of the output has a plurality of
drivers, and I suspect they're interacting in non-obvious ways.

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