[Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=421

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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           Assignee|lkcl at lkcl.net               |kc5tja at arrl.net

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/trap/main_stage.py;hb=HEAD

if you look at the fixedtrap wiki page containing the pseudocode, traps
nominally in PowerISA do testing of 5 bits.  however what we have added here is
an unofficial "microcoding" system using two extra parameters to the Record
OpSubset: traotype and trapaddr.

traptype when set will make an *unconditional* trap that *does not* need RA or
RB.

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