[Libre-soc-bugs] [Bug 418] SPR pipeline formal correctness proof needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=418

--- Comment #3 from Samuel A. Falvo II <kc5tja at arrl.net> ---
There is so much meta-programming happening, I cannot navigate the interface of
the SPR main stage module.  Is there some place I can go to read up on how
interfaces are constructed and what their signal meanings are?  E.g., what is
the difference between spr1 and fast1?  Where does the op field come from? 
Etc.  Thanks.

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