[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=412

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/examples/
> simplesoc_ecp5.py
> not quite the same thing, may prove useful.

contains a UART example which should do well after adaptation, for the
helloworld test.

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