[Libre-soc-bugs] [Bug 323] create POWER9 MUL pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=323

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 512e2d72912ba57913ab1b1297a085d5fae67181 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Thu Jul 9 10:52:46 2020 +0100

    add new stages etc. to get multiply working without xer_ca

removing xer_ca from the DIV and MUl pipelines (both on input and
output) needs a bit of tweaking.

it's important because unnecessary registers being read/written to
creates dependencies that create chaining and prevent opportunities
for parallelism.

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