[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #53 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #48)
> (In reply to Jacob Lifshay from comment #44)
> > (In reply to Luke Kenneth Casson Leighton from comment #41)
> > > btw jacob i noticed that on qemu, divw sets RT=RA when RB=0.
> > > 
> > > can you check that behaviour on POWER9?
> > 
> > IIRC, on POWER9, division by zero results in RT=0 for all div*/mod*
> > instructions. I specifically included that as a test case in
> > power-instruction-analyzer since that's a case where the result is undefined
> > according to the PowerISA spec. For divwo, see:
> > https://salsa.debian.org/Kazan-team/power-instruction-analyzer/-/blob/
> > 13dae100c6bc5685059195010ceb46ae68b9f306/src/instr_models.rs#L153
> 
> qemu definitely sets RT=RA for divw when RB=0.  note: not divwo - *divw*.
> 
> which is why i asked if you could check.  hugh and paul mackerras mentioned
> that this *might* have been old behaviour on e.g. POWER7 or POWER8.

I just updated power-instruction-analyzer to include all div*[o][.] variants,
they all match the original instr_models.rs -- all of `divw`, `divwo`, `divw.`,
and `divwo.` all provide the exact same results when tested on POWER9.

So, unless we made a mistake somewhere, qemu doesn't match POWER9's behavior
(which is to be expected, since that part is undefined).

I also added all instructions to the Python API, so you can just call the
functions in instr_model.rs:
(requires a recent version of Rust -- a nightly version is no longer required
since PyO3 v0.11)

$ git clone https://salsa.debian.org/Kazan-team/power-instruction-analyzer.git
$ source <path-to-venv>/bin/activate
$ cd power-instruction-analyzer
$ pip install .
$ python
>>> import power_instruction_analyzer as pia
>>> inputs = pia.InstructionInput(ra=0x1234, rb=0, rc=0)
>>> print(pia.divw(inputs))
>>> print(pia.divwo(inputs))
>>> print(pia.divw_(inputs))
>>> print(pia.divwo_(inputs))

it will output (last output line split over two lines:
{"rt":"0x0"}
{"rt":"0x0","so":true,"ov":true,"ov32":true}
{"rt":"0x0","cr0":{"lt":false,"gt":false,"eq":true,"so":false}}
{"rt":"0x0","so":true,"ov":true,"ov32":true,
"cr0":{"lt":false,"gt":false,"eq":true,"so":true}}

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