[Libre-soc-bugs] [Bug 362] improvements to nmigen and yosys

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=362

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
also needed is a way for yosys (or nmigen) to optimise out constants and unused
signals... *without* requiring that the entire design be flattened.

currently, coriolis2 has had to be significantly modified to cope with dangling
(unused) connections.  the design is too big to flatten so it is not
appropriate to call yosys flatten.

when the design is not flattened, module parameters can be Const or unused. 
when a design is flattened this is not a problem.

however without flattening yosys will *not* pass the Const parameter into the
module and perform constant optimisation *in the module*, and it will *not*
likewise remove unused outgoing signals *from* that module that are not
externally connected to its parent.

when such non-optimised non-flattened designs are passed to coriolis2 it causes
problems because of dangling (unconnected) signals.

two potential ways in which this can be fixed: in yosys, or on nmigen.

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