[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #4 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> that sounds about right.  if you can use nmigen with FSM, like in this
> example: https://github.com/nmigen/nmigen/blob/master/examples/basic/fsm.py

Sure.

> ah ok so instead of just going straight into "START" in the "DONE" phase
> (line 51) it would check if n.ready_i?  wait... actually... "ack" would
> be renamed "n.valid_o" and "self.rdy" would be renamed "n.ready_i", right?

Indeed. And forget the ERROR state.

But it's the reverse: self.rdy is n.valid_o and self.ack is n.ready_i.

> and at line 29, ~self.i would be called "p.valid_i" and an extra thing
> added to set p.ready_o for one cycle (combinatorial), right?

Indeed, p.ready_o will be set high, combinatorially, at START.

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