[Libre-soc-bugs] [Bug 407] XICS interrupt controller is needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=407

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=nmigen-soc.git;a=blob;f=nmigen_soc/test/test_csr_wishbone.py;h=2cde268d2b2075d62a54fe7c382a3c65287f6118;hb=87c34e8c810dc4f148be1af8b238b610dc808141


use nmigen-soc registers, should work well

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