[Libre-soc-bugs] [Bug 413] DIV "trial" blocks are too large

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=413

--- Comment #17 from Jacob Lifshay <programmerjake at gmail.com> ---
your pipeline loopback solution is waay more complex then I was imagining:
The pipeline would have either 7 stages (for 1x radix 3 compute stage per
pipeline stage and 1 extra stage at each end for leftovers) or about 3 or 4
(for 2x radix 3 compute stages per pipeline stage).
I think we should only have 10 or so reservation stations for the non-SIMD
case, since we don't need much more than the number of instructions that can be
simultaneously executing. 20 or 30 is excessive.
There would be a 2-bit Signal tracking the loop number -- totally separate from
anything in ctx. fiddling with the id seems like a horrible mess that can be
easily avoided. We would build a custom loop header and footer pipeline control
stages, where they are constructed together so can send signals from footer to
header for the loop backedge. This would also be useful for fsm pipelines since
we could implement that using only a combinatorial stage in between the loop
header and footer.


So, the pipeline would look kinda like:

RS0    RS1 ... RS9
 |      v      |
 | +----+----+ |
 +>+Prio. Sel+<+
   +----+----+
        |
        v
   +----+----+
   |  setup  |
   +----+----+
        |
        v
   +----+----+
+->+ loop hdr|
|  +----+----+
|       |
|       v
|  +----+----+
|  | compute0|
|  +----+----+
|       |
|       v
|  +----+----+
|  | compute1|
|  +----+----+
|       |
|      ...
|       |
|       v
|  +----+----+
|  | compute5|
|  +----+----+
|       |
|       v
|  +----+----+
+--+ loop ftr|
   +----+----+
        |
        v
   +----+----+
   |  finish |
   +----+----+
        |
        v
   back to RSes

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