[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #51 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #48)
> (In reply to Jacob Lifshay from comment #44)
> > (In reply to Luke Kenneth Casson Leighton from comment #41)
> > > btw jacob i noticed that on qemu, divw sets RT=RA when RB=0.
> > > 
> > > can you check that behaviour on POWER9?
> > 
> > IIRC, on POWER9, division by zero results in RT=0 for all div*/mod*
> > instructions. I specifically included that as a test case in
> > power-instruction-analyzer since that's a case where the result is undefined
> > according to the PowerISA spec. For divwo, see:
> > https://salsa.debian.org/Kazan-team/power-instruction-analyzer/-/blob/
> > 13dae100c6bc5685059195010ceb46ae68b9f306/src/instr_models.rs#L153
> 
> qemu definitely sets RT=RA for divw when RB=0.  note: not divwo - *divw*.
> 
> which is why i asked if you could check.  hugh and paul mackerras mentioned
> that this *might* have been old behaviour on e.g. POWER7 or POWER8.

Ok, I'll check once I write the code. I was assuming that the div*o
instructions produced the same results as all other div* variants. I'll also
check "div*." and "div*o." variants (which I find their naming to be annoying
due to confusion with the end of a sentence).

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