[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #46 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
On Thu, Jul 2, 2020 at 8:36 PM bugzilla-daemon--- via libre-soc-bugs
<libre-soc-bugs at lists.libre-riscv.org> wrote:

> No, self.o.op.eq() was intended to copy the PowerISA opcode since that's needed
> after DivPipeCore finishes its work.

i said already: it doesn't exist.  self.o.op does not exist.  if you ran the
unit test as i suggested, you would have found this out.


> Notice that CoreInputData derives from
> CoreBaseData, which derives from DivInputData,

which derives from IntegerData, which contains "ctx" (pipeline context).
ctx contains "op", which is where the operation information comes from


> which should contain a field for
> the PowerISA opcode, which is what I assumed self.o.op is.

self.i.ctx (and self.o.ctx) contains the internal op from PowerDecode2,
actually a subset (CompTrapOpSubset).

therefore, this gets the InternalOp (a member of CompTrapOpSubset):

        # convenience variables
        op, a, b = self.i.ctx.op, self.i.a, self.i.b

and therefore this copies the operation subset information needed
down the pipeline chain:

        ###### sticky overflow and context, both pass-through #####

        comb += self.o.xer_so.eq(self.i.xer_so)
-->     comb += self.o.ctx.eq(self.i.ctx)        <----

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